Can you guarantee correctness of the constraints on your most recent SOC?
We guarantee constraints generation for the entire chip and/or any layer of hierarchy for any mode, in one day or less... This is the Excellicon Challenge!
Problems We Solve...
More than 70% of the SOC designs are delayed and some 25% of the micro-chips fail, due to timing constraints problems, yet there is no comprehensive commercially available constraints solution; until today. Today design teams spend many man months on defining, refining, and maintaining timing constraints.
At the same time the timing information which has historically not been utilized at the intial design coding stage is crucial for analysis of many downstream tools used by designers.
Unfortunately it is hard to quantify the exact amount of time spent on constraints definition and preparing and data refinement for analysis as well as downstream setup process. The process is fragmented and spread throughout the design cycle costing many man weeks of manual effort .
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Problem with Constraints tools and Flawed Survey... Excellicon products from users perspective on ESNUG - Comprehensive Eval Report ...
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July 2014 - Excellicon is part of Synopsys Via Access Program