Excellicon - Timing Closure Done Once! Done Right!

Welcome to Excellicon
Timing Closure... Done Once! Done Right!

Excellicon provides Electronic Design Automation (EDA) software tools targeted at solving complex problems associated with timing closure of multimillion gates SOC designs. SOC design involves correct construction of a set of functionalities and associated timings. Excellicon software based on patented technology enables designers to compile, manage, verify, analyze, and propagate timing information from start to the end of SOC design cycle all in a simple to use intuitive environment.

Our belief is that through a systematic approach to timing constraints development, the entire development schedule can be more predictable and better optimized for faster, more efficient product delivery.

Excellicon Advantage
Solving Timing Closure Complextity...

Next-generation constraints development technology employing patented formal based technology which provides capability to seamlessly generate correct timing constraints, as well as tools to verify existing timing constraints for accuracy and correctness.

Using Excellicon products, all the SoC modes can be detected automatically, eliminating months of iterations. All timing constraints data is maintained in a single portable and traceable database. Maintaining continuity between early design development and implementation thus ensuring design intent convergence, while focusing on power and area savings. What you simulate is…..What you implement.

Can you guarantee correctness of the constraints on your most recent SOC?

We guarantee constraints generation for the entire chip and/or any layer of hierarchy for any mode, in one day or less... This is the Excellicon Challenge!

Problems We Solve...

More than 70% of the SOC designs are delayed and some 25% of the micro-chips fail, due to timing constraints problems, yet there is no comprehensive commercially available constraints solution; until today. Today design teams spend many man months on defining, refining, and maintaining timing constraints. Unfortunately it is hard to quantify the exact amount of time spent on constraints definition and refinement as the process is fragmented and spread throughout the design cycle.